1. Field of the Invention
The present invention relates to a communication system for transmitting real time data, e.g., video data and audio data, with employment of the communication control bus such as the serial bus standardized by IEEE-P1394 (referred to as a "P1394 serial bus" hereinafter).
2. Description of the Related Art
A communication system is conceivable such that a plurality of electronic appliances are connected to each other by means of the communication control bus such as the P1394 serial bus, and both digital information signals and control signals are communicated among these electronic appliances.
In FIG. 3, there is shown an example of such a system. This system comprises electronic appliances A, B, C connected to each other by means of the P1394 serial bus. These electronic appliances are, for instance, a digital VTR, a tuner, a monitor and the like. The respective electronic appliances include a circuit with an essential function of, for example, a recording/reproducing unit for a digital VTR and a display unit for a monitor in addition to a circuit for transmitting/receiving a signal by means of the P1394 serial bus.
A data transmission is carried out among the electronic appliances A to C which commonly share the P1394 serial bus every predetermined communication cycle, as illustrated in FIG. 4. With respect to the management of the communication cycle, a predetermined electronic appliance for managing the communication system, for instance, the electronic appliance A, transfers the cycle start data indicative of the starting time of the communication cycle by means of the P1394 bus to other electronic appliances, so that the data transmission in this communication cycle is commenced.
The time information on the P1394 serial bus is managed by a timer register used by each of these electronic appliances. The timer registers employed in the respective electronic appliances use internal clocks to produce the time information. This time information is reset on the basis of the timing of the cycle sync every 125 microseconds (see FIG. 4). Then, this time information is corrected based on the time information given to the cycle start data.
As a data format transmitted within one communication cycle, there are two sorts of data format, i.e., a synchronous type data packet such as video data and audio data, and an asynchronous type data packet such as a connection control command. Then, the synchronous type data packet is transmitted prior to the asynchronous type data packet. FIG. 4 represents only the synchronous type data packet.
In the communication system with such an arrangement, when the communication cycle is repeated every 125 microseconds under ideal conditions, the time period at which the timer registers employed in the respective electronic appliances are reset is coincident with that of the cycle start data. However, when the transmission time of the asynchronous type data packet is prolonged, since the timing at which the next communication cycle is commenced is delayed, the timing of the cycle start data is delayed, as compared with that of the cycle sync.
Considering a case like the above-described communication system, both of the video data and the audio data (referred to as "AV data" hereinafter), which are output by the digital VTR, are transmitted to another video VTR.
FIG. 5 represents a model of the AV data packeted for transmission. The AV data reproduced by the digital VTR are arranged as an array of data blocks having constant sizes, as shown in FIG. 5, which arrive at the transmitter circuit. This data block process is performed by using a FIFO method, or first-in first-out method, employed between the recording/reproducing unit of the digital VTR and the transmitter circuit. The data blocks received by this transmitter circuit are numbered according to the serial data block number, and are packeted in the unit of a data block, and then the packeted data blocks are sent out to the data bus. At this time, the data blocks which have been received during a time period from one preceding cycle sync to the present cycle sync are packeted in accordance with the data block numbers from the lower numbers to the higher numbers, and then the packeted data blocks are transmitted after the cycle start data.
In FIG. 5, since the data blocks are received by the transmitter circuit during an interval of approximately 50 microseconds, when normal communication is carried out, the number of data blocks transmitted by one packet is equal to either 2 or 3.
Furthermore, referring now to FIG. 8, another concrete example of such a communication system will be explained. This communication system is equipped with a TV, a VTR 1, a VTR 2, and a camcorder (referred to as a "CAM" hereinafter) as the AV appliance. Then, the P1394 serial buses capable of transmitting the digital AV signal and the control signal in the mixture state are employed to connect the CAM with the TV, the TV with the VTR 1, and the VTR 1 with the VTR 2. Each of these appliances has the function of relaying the control signal and the digital AV signal to the P1394 serial bus.
FIG. 9 is a block diagram for indicating a basic arrangement of a VTR corresponding to one example of the AV electronic appliance employed in the communication system of FIG. 8. This VTR includes, as the basic components of the VTR, a deck unit 1, a tuner unit 2, an operation unit 3 functioning as a user interface, a display unit 4, and a microcomputer 5 for controlling the overall operations of the VTR, for producing a packet (described hereinafter), and for holding an address. This VTR further comprises a digital interface (referred to as a "digital I/F" hereinafter) 6 for the P1394 serial bus, and a switch box unit 7 for switching signals among the deck unit 1, the tuner unit 2, and the digital I/F 6.
It should be noted that when a TV is employed as the AV appliance, a monitor unit and an amplifier unit are used instead of the deck unit 1, and no display unit 4 is employed. In case of a CAM, a camera unit is provided instead of the tuner unit 2.
As illustrated in FIG. 10, a data transmission is performed in a preselected communication cycle (for example, 125 microseconds) in the communication system of FIG. 8. Then, both of the synchronous communication and the asynchronous communication can be carried out. In the synchronous communication, the data signal such as the digital AV signal is continuously transmitted at a constant data rate, whereas in the asynchronous communication, the control signal such as the connection control command is irregularly transmitted, if required.
The cycle start packet CSP is present at the beginning of the communication cycle, and subsequently, a time period is set during which the packet for the synchronous communication is transmitted. The channel numbers 1, 2, 3, . . . , N are attached to the respective packets for performing the synchronous communication, so that a plurality of synchronous communications can be achieved.
Assuming now that the channel 1 is allocated to the communication performed from the CAM to the VTR 1, the CAM transmits the synchronous communication packet attached with the channel number 1 just after the cycle start packet CSP, the data bus is monitored by the VTR 1, and then the synchronous communication packet attached with the channel number 1 is acquired to perform the communication. Furthermore, when the channel 2 is allocated to the communication from the VTR 2 to the TV, both of the communication from the CAM to the VTR 1 and the communication from the VTR 2 to the TV can be carried out in a parallel manner.
Then, after the transmission of the synchronous communication packets for all of the channels have been completed, the time period up to the next cycle start packet CSP is used as the asynchronous communication. In FIG. 10, packets A and B correspond to the asynchronous communication packets.
In the communication system with employment of the P1394 serial bus, when the respective AV electronic appliances are connected to each other by means of the serial buses, the node ID (physical address) is automatically allocated in accordance with these connection conditions. In the case of FIG. 8, symbols #0 to #3 correspond to the node ID. Next, the allocating sequence of the node ID will be simply explained with reference to FIG. 11.
In FIG. 11, such a hierarchical structure is made that a leaf node B and a branch node C are connected to the lower grade of the route node A, and further, a leaf node D and a leaf node E are connected to the lower grade of the branch node C. In other words, the node A corresponds to the parent node for the nodes B and C, and the node C corresponds to the parent node for the nodes D and E. First, a description will be made of the sequence for determining this hierarchical structure.
When a twist-pair cable of the P1394 serial bus is used to connect the nodes A and B, the nodes A and C, and the nodes C and E, the node in which only one input/output port is connected to another node transfers such a message to the other node that the counter node with only one input/output part corresponds to the parent node. The term "counter node" may be defined as the node connected to the present node.
In the case of FIG. 11, the node B transfers such a message that node B corresponds to the parent node for port 1 of the node A, the node D transfers such a message that node D corresponds to the parent node for the port 2 of the node C, and the node E transfers such a message that node E corresponds to the parent node of port 3 of the node C.
As a result, when the node A recognizes that the child node is connected to the port 1, the port 1 notifies the node B that it corresponds to the child node. Also, the node C notifies from the port 2 thereof to the node D that it corresponds to the child node, and notifies from the port 3 thereof to the node E that it corresponds to the child node.
Then, the nodes having a plurality of input/output ports are connected to other nodes transfer messages that the counter nodes correspond to the parent node and with respect to nodes other than the nodes to which such a message has been transferred, that they are the parent nodes.
In the case of FIG. 11, the node C sends to the port 2 of node A a message that the node A corresponds to the parent node, and the node A sends to the port 1 of the node C such a message that the node C corresponds to the parent node. At this time, since the counter nodes will send between the node A and the node C such messages that they correspond to the parent nodes, the node which first receives a message that it corresponds to the parent node becomes the parent node.
If the counter nodes transfer at the same time such messages that they are the parent nodes, then after the nodes wait for a period of time set at random by the respective nodes, the counter nodes then send messages that they are the parent nodes. FIG. 11 indicates such a case that the node A becomes the parent node.
It should be noted that in the above description, the nodes B, D, E whose single input/output port is connected to an other node transfer such a message that the counter node corresponds to the parent node with respect to the part connected to its own node. Alternatively, for instance, when the timing for the node B to transfer the message that the node A corresponds to the parent node is delayed, and the node B has transferred in advance the message that the node A corresponds to the parent, the node B becomes the route node.
Subsequently, a description will now be made of the sequence to apply the physical addresses to the respective nodes. Basically, a physical address of a node is applied in such a manner that a parent node assign a physical address to a child node. When there are a plurality of child nodes, for example, the parent node will apply the physical addresses to such child nodes which are connected to the lower port numbers.
In FIG. 11, when the node B is connected to the port 1 of the node A and the node C is connected to the port 2, the node A applies the physical address to the node B. The node B transmits to the bus the data for indicating that the node ID#0 has been assigned to its own node B.
Next, the node A determines the address with respect to the node C. The node C assigns the address to the node D connected to the port 2 of node C. The node D assigns the node ID#1 to its own node.
Subsequently, the node C applies the physical address to the node E connected to the port 3 of node C. The node E assigns the node ID#2 to its own node E. When the node C has completed the address assignments to the child nodes D and E, the node C assigns the node ID#3 to its own node C.
It should be noted that a detailed description about the P1394 serial bus involving the sequence to allocate this node ID is disclosed as "IEEE P1394 Serial Bus Specification" (issued on Oct. 14, 1993).
There are four prior patent applications:
1). EPC Laid-open No. 0614297, PA1 2). Japanese Patent Application No. 5126682, PA1 3). Japanese Patent Application No. 5200055, PA1 4). Japanese Patent Application No. 6051246,
and the corresponding U.S. patent applications are still pending.
When the AV data is transmitted in such a way, as shown in FIG. 6, if the cycle start data is dropped out due to noise appearing on the bus and the bus reset operation, then the data blocks 2 and 3 would be dropped out which should be originally transmitted in the communication cycle commenced from this cycle start data. This is because the protocol for the P1394 serial bus determines that after the cycle start data has been detected, the data block is transmitted.
Accordingly, as illustrated in FIG. 7, in order that the data blocks are not dropped out even when the cycle start data is dropped out, the data blocks 2 and 3 which should be originally transmitted in the communication cycle starting with the dropped cycle start data may be transmitted in the communication cycle commenced from the next normal cycle start data. Since the total number of data blocks transmitted as a single data packet is increased to 5, however, the operation frequency band (bus occupation time) would also be increased. If more than two cycle start data would be consecutively dropped out, then a total number of data blocks transmitted as a single data packet will be further increased, that is the operation frequency band will be further increased. As a result, there is such a problem that the frequency band could not be effectively utilized.
The present invention has been made to solve such a problem, and therefore has an object to provide a communication system capable of effectively using a frequency band. Also, the present invention has another object to provide a communication system capable of preventing a dropout of a data block, and further, capable of effectively using a frequency band.